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march 2014 altera corporation ds-1043 datasheet ? 2014 altera corporation. all rights rese rved. altera, arria, cyclone, enpiri on, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera cor poration and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademar ks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current spec ifications in accordance with altera's standard warranty, but reserves the right to make cha nges to any products and services at any time without notice. alt era assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein exce pt as expressly agreed to in writing by altera. altera customers are advised to obtain th e latest version of device specifications before relying on a ny published information and before placing or ders for products or services. 101 innovation drive san jose, ca 95134 www.altera.com subscribe iso 9001:2008 registered enpirion ? power datasheet EC7100VQI pwm dc/dc controller with vs inputs for fpga power regulator the altera? enpirion? ec 7100vqi is a single-phase synchronous-buck pwm controller. the wide 3.3v to 25v input voltage range is ideal for systems that run on battery or ac- adapter power sources. the ec7100 vqi is a low-cost solution for applications requiring dynamicall y selected slew-rate controlled output voltages. the soft-start and dynamic setpoint slew-rates are capacitor programmed. voltage iden tification logic- inputs select four resistor-programmed setpoint reference voltages that directly set the output voltage of the conve rter between 0.5v and 1.5v, and up to 5v with a feedback voltage divider. the EC7100VQI modulator has equi valent light-loa d efficiency, faster transient performance, accurately regulated frequency control and all internal compensation. these updates, together with integrated mosfet driver s and schottky bootstrap diode, allow for a high-performance regula tor that is highly compact and needs few external components. the EC7100VQI has differential remote sensing for output voltage and selectable switching frequency. for maximum efficiency , the converter automatically enters diode-emulation mode (d em) during light-load conditions such as system standby. features ? input voltage range: 3.3v to 25v ? output voltage range: 0.5v to 5v ? precision regulation - frequency control loop - 0.5% system accuracy over -10c to +100c ? optimal transient response ? output remote sense ? extremely flexible output voltage programmability - 2-bit vs selects four independent setpoint voltages - simple resistor programming of setpoint voltages ? selectable 300khz, 500khz, 600kh z or 1mhz pwm frequency in continuous conduction ? automatic diode emulation mode for highest efficiency ? power-ok monitor for soft-start and fault detection applications ? fpga power ? digital processor power ? mixed-signal asic power figure 1. EC7100VQI application schematic with four output voltage setpoints and dcr current sense vsns boot ugate sw en pok fsw nsns vs1 vs0 sref set0 set1 avin1 avin2 l o c boot c sen r ocp q hs q ls 3.3v to 25v 0.5v to 5v r o co cin v in v out c soft c avin2 +5v r avin2 c avin1 gpio 1 2 3 4 5 6 15 14 13 12 11 18 9 10 17 r pok pgnd lgate 16 7 8 20 19 r set1 r set2 r set3 r set4 r fb r ofs set2 fb ocp nsns1 r ofs1 r fb1 nsns1 gnd 0 09613 march 14, 2014 rev a
page 2 EC7100VQI pwm dc/dc controller with vs inputs fo r fpga power regulator march 2014 altera corporation applications sche matics: EC7100VQI ordering information part number (note 2) part marking temp range (c) package (pb-free) pkg. dwg. # EC7100VQI (note 1) 7100 -10 to +100 20 ld 3x4 qfn l20.3x4 notes: 1. these altera enpirion pb-free plastic pack aged products employ special pb-free materi al sets, molding comp ounds/die attach ma terials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free sold ering oper- ations). altera enpirion pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-fre e requirements of ipc/jedec j std-020. figure 2. EC7100VQI application schematic with four output voltage setpoints and resistor current sense vsns boot ugate sw en pok fsw nsns vs1 vs0 sref set0 set1 avin1 avin2 l o c boot c sen r ocp q hs q ls 3.3v to 25v 0.5v to 5v r o co cin v in v out c soft c avin2 +5v r avin2 c avin1 gpio 1 2 3 4 5 6 15 14 13 12 11 18 9 10 17 r pok pgnd lgate 16 7 8 20 19 r set1 r set2 r set3 r set4 r fb r ofs set2 fb ocp r sen nsns1 r ofs1 r fb1 nsns1 gnd 0 09613 march 14, 2014 rev a
page 3 EC7100VQI pwm dc/dc controller with vs inputs for fpga power regulator march 2014 altera corporation block diagram figure 3. simplified functional block diagram of EC7100VQI driver driver boot ugate sw avin1 lgate pgnd overcurrent overvoltage/ soft-start circuitry modulator dead-time generation pok circuitry reference voltage circuitry por vsns ocp set 0 set 1 set2 vs1 vs0 fb pok sref avin2 nsns en internal compensation amplifier + gnd remote sense circuitry fsw fs selection circuitry undervoltage 09613 march 14, 2014 rev a
page 4 EC7100VQI pwm dc/dc controller with vs inputs fo r fpga power regulator march 2014 altera corporation pin configurations EC7100VQI (20 ld 3x4 qfn) top view 10 vsns 9 ocp 8 fb 7 set2 4 sref 3 vs0 1 2 20 pgnd 19 lgate 18 avin1 17 avin2 nsns vs1 5 6 set0 set1 16 15 14 13 boot ugate sw en 12 11 pok fsw gnd 09613 march 14, 2014 rev a
page 5 EC7100VQI pwm dc/dc controller with vs inputs for fpga power regulator march 2014 altera corporation EC7100VQI functional pin descriptions pin number symbol description 1n s n s negative remote sense input of v out . if resistor divider consisting of r fb and r ofs is used at fb pin, the same resistor divider should be used at nsns pin, i.e. keep r fb1 =r fb , and r ofs1 =r ofs . 2v s 1 logic input for setpoint vol tage selector. use in conj unction with the vs0 pin to select among four setpoint reference voltages. 3v s 0 logic input for setpoint voltage selector. use in conjun ction with the vs1 pin to se lect among four setpoint reference voltages. 4s r e f soft-start and voltage slew-rate programming capacito r input and setpoint reference voltage programming resistor input. connects internally to the inverting input of the v set voltage setpoint amplifier. 5s e t 0 voltage set-point programming resistor input. 6s e t 1 voltage set-point programming resistor input. 7s e t 2 voltage set-point programming resistor input. 8f b voltage feedback sense input. connects internally to the inverting input of the control- loop error transconductance amplifier. the convert er is in regulation when the voltage at the fb pin equals the voltage on the sref pin. 9o c p input for the overcurrent detection circuit. th e overcurrent setpoint programming resistor r ocp connects from this pin to the sense node. 10 vsns output voltage sense input for the modulator. the vsns pin also serv es as the reference input for the overcurrent detection circuit. 11 fsw input for programming the regulator switching frequency. pull this pin to avin2 for 1mhz switching. pull this pin to gnd with a 100k ? resistor for 600khz switching. leave this pin floating for 500khz switching. pull this pin directly to gnd for 300khz switching. 12 pok power-ok open-drain indicator output. this pin changes to high impedan ce when the conver ter is able to supply regulated voltage. 13 en enable input for the ic. pulling en above the rising thres hold voltage initializes the soft-start sequence. 14 sw return current path for the ugate high-side mosfet driver, v in sense input for the modulator, and inductor current polar ity detector input. 15 ugate high-side mosfet gate driver out put. connect to the gate terminal of the high-side mosfet of the converter. 16 boot positive input supply for the ugate high-side mosfet gate driver. the boot pin is internally connected to the cathode of the schottky boot-strap diode. connect an mlcc between the boot pin and the sw pin. 17 avin2 input for the ic bias voltage. conn ect +5v to the avin2 pin and decouple with at least a mlcc to the gnd pin. 18 avin1 input for the lgate and ugate mosfet driver circuits . the avin1 pin is internally connected to the anode of the schottky boot-strap diode. connect +5v to the avin1 pin and decouple with a mlcc to the pgnd pin. 19 lgate low-side mosfet gate driver outp ut. connect to the gate terminal of the low-side mosfet of the converter. 20 pgnd return current path for the lgate mosfet driver . connect to the source of the low-side mosfet. bottom pad gnd ic ground for bias supply and signal reference. 09613 march 14, 2014 rev a
page 6 EC7100VQI pwm dc/dc controller with vs inputs fo r fpga power regulator march 2014 altera corporation absolute maximum ratings thermal information avin2, avin1, pok, fsw to gnd. . . . . . . . . . . . . -0.3v to +7.0v avin2, avin1to pgnd . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7.0v gnd to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v en, set0, set1, set2, vsns, vs0, vs1, fb, nsns, ocp, sref . . -0.3v to gnd, avin2 + 0.3v boot voltage (v boot-gnd ). . . . . . . . . . . . . . . . . . . . . .-0.3v to 33v boot to sw voltage (v boot-sw ) . . . . . . . . . . . . -0.3v to 7v (dc) -0.3v to 9v (<10ns) sw voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 28v gnd -8v (<20ns pulse width, 10j) ugate voltage . . . . . . . . . . . . . . . . . . . .v sw - 0.3v (dc) to v boot v sw - 5v (<20ns pulse width, 10j) to v boot lgate voltage . . . . . . . . . . . . gnd - 0.3v (dc) to avin2 + 0.3v . . . . . . . . . gnd - 2.5v (<20ns pulse width, 5j) to avin2 + 0.3v esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . 2kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . 200v charged device model . . . . . . . . . . . . . . . . . . . . . . . 1kv latch up . . . . . . . . . . . . . . . . jedec class ii level a at +125c thermal resistance (typical) ? ja (c/w) ? jc (c/w) 16 ld tqfn (note 2) . . . . . . . . . 90 n/a 20 ld tqfn (note 2) . . . . . . . . . 88 n/a 20 ld qfn (notes 3, 4) . . . . . . . . . 44 5 junction temperature range . . . . . . . . . . . . . . . . . . -55 ? c to +150 ? c operating temperature range: EC7100VQI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +100c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? recommended operating conditions ambient temperature range: EC7100VQI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +100c converter input voltage to gnd . . . . . . . . . . . . . . . . . . 3.3v to 25v avin2, avin1 to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5v 5% caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 2. ? ja is measured with the co mponent mounted on a high effective ther mal conductivity test board in free air. 3. ? ja is measured in free air with the compon ent mounted on a high effectiv e thermal conductivity test bo ard with ?direct attach? fe atures. 4. for ? jc , the ?case temp? location is the center of th e exposed metal pad on the package underside. electrical specifications all typical specifications t a = +25c, avin2 = 5v. boldface limits apply over the operating temperature range, -40c to +100c, unless otherwise stated. parameter symbol test conditions min (note 7) typ max (note 7) unit avin2 and avin1 avin2 input bias current i avin2 en = 5v, avin2 = 5v, fb = 0.55v, sref < fb -1.21.9ma avin2 shutdown current i avin2off en = gnd, avin2 = 5v -01.0a avin1 shutdown current i avin1off en = gnd, avin1 = 5v -01.0a avin2 por threshold rising avin2 por threshold voltage v avin2_thr 4.40 4.52 4.60 v falling avin2 por threshold voltage v avin2_thf 4.10 4.22 4.35 v regulation system accuracy vs0 = vs1 = avin2, pwm mode = ccm -0.5 - +0.5 % vs0 = vs1 = avin2, pwm mode = ccm -0.75 +0.5 % pwm switching frequency accuracy f sw pwm mode = ccm -15 - +15 % pwm mode = ccm -22 - +15 % vsns vsns input impedance r vsns en = 5v -600- k ? vsns reference offset current i vsns v enthr < en, sref = soft-start mode -8.5-a vsns input leakage current i vsnsoff en = gnd, vsns = 3.6v -0-a 09613 march 14, 2014 rev a
page 7 EC7100VQI pwm dc/dc controller with vs inputs for fpga power regulator march 2014 altera corporation error amplifier fb input bias current i fb en = 5v, fb = 0.50v -20 - +50 na sref (note 5) soft-start current i ss sref = soft-start mode 8.5 17 25.5 a voltage step current i vs sref = setpoint-stepping mode 51 85 119 a sref = setpoint-stepping mode 46 85 127 a power ok pok pull-down impedance r pok pok = 5ma sink -50150w pok leakage current i pok pok = 5v -0.11.0a gate driver ugate pull-up resistance r ugpu 200ma source current -1.11.7w ugate source current i ugsrc ugate - sw = 2.5v -1.8- a ugate sink resistance r ugpd 250ma sink current -1.11.7w ugate sink current i ugsnk ugate - sw = 2.5v -1.8- a lgate pull-up resistance r lgpu 250ma source current -1.11.7w lgate source current i lgsrc lgate - gnd = 2.5v -1.8- a lgate sink resistance r lgpd 250ma sink current -0.551.0w lgate sink current i lgsnk lgate - pgnd = 2.5v -3.6- a ugate to lgate deadtime t ugflgr ugate falling to lgate rising, no load -21- ns lgate to ugate deadtime t lgfugr lgate falling to ugate rising, no load -21- ns sw sw input impedance r sw -33-k ? bootstrap diode forward voltage v f av i n 1 = 5 v, i f = 2ma -0.58- v reverse leakage i r v r = 25v -0-a control inputs en high threshold voltage v enthr 2.0 - - v en low threshold voltage v enthf --1.0v en input bias current i en en = 5v 0.85 1.7 2.55 a en leakage current i enoff en = gnd -01.0a vs<0,1> high threshold voltage v vsthr 0.65 - - v vs<0,1> low threshold voltage v vsthf --0.5v vs<0,1> input bias current i vs en = 5v -0.5-a vs<0,1> leakage current i vidoff en=0v -0-a protection ocp threshold voltage v ocpth v ocp - vsns -1.75 - 1.75 mv electrical specifications all typical specifications t a = +25c, avin2 = 5v. boldface limits apply over the operating temperature range, -40c to +100c, unless otherwise stated. (continued) parameter symbol test conditions min (note 7) typ max (note 7) unit 09613 march 14, 2014 rev a
page 8 EC7100VQI pwm dc/dc controller with vs inputs fo r fpga power regulator march 2014 altera corporation theory of operation the following sections will prov ide a detailed description of the inner workings of the EC7100VQI. power-on reset the ic is disabled until the voltage at the avin2 pin has increased above the ri sing power-on re set (por) thre shold voltage v av i n 2 _ t h r . the controller will become di sabled when the voltage at the avin2 pin decreases below the falling por threshold voltage v av i n 2 _ t h f . the por detector has a noise filter of appr oximately 1s. start-up timing once avin2 has ramped above v avin2_thr , the controller can be en abled by pulling the en pin vo ltage above the input-high threshold v enthr . approximately 20s later, the voltage at the sref pi n begins slewing to the desi gnated vs set-point. the converter output voltage at the fb feedback pin follows the voltage at the sref pin. during so ft-start, the regulator always operates in ccm until the soft-start sequence is complete. start-up and voltage-step operation when the voltage on the avin2 pin has ramped above the rising power-on reset voltage v av i n 2 _ t h r , and the voltage on the en pin has increased above the rising enable threshold voltage v enthr , the sref pin releases its di scharge clamp and enables the reference amplifier v set . the soft-start current i ss is limited to 17a and is sourced out of the sref pin into the parallel rc network of capacitor c soft and resistance r t . the resistance r t is the sum of all th e series connected r set programming resistors and is written as equation 1: the voltage on the sref pin rises as i ss charges c soft to the voltage reference setpoint selected by the state of the vs inputs at the time the en pin is asserted. the regul ator controls the pwm such that the voltage on the fb pin tracks the rising voltage on the sre f pin. once c soft charges to the selected setpoint voltage, the i ss current source comes out of the 17a current limit and deca ys to the static value set by v sref /r t . the elapsed time from when the en pin is asserted to when v sref has reached the voltage reference setpoint is the soft-start delay t ss which is given by equation 2: ocp reference current i ocp en = 5.0v 7.65 8.5 9.35 a en = 5.0v 7.05 8.5 9.35 a ocp input resistance r ocp en = 5.0v -600- k ? ocp leakage current i ocp en = gnd -0-a uvp threshold voltage v uvth v fb = %v sref 81 84 87 % ovp rising threshold voltage v ovrth v fb = %v sref 113 116 120 % v fb = %v sref 112.5 116 120 % ovp falling threshold voltage v ovfth v fb = %v sref 98 102 106 % otp rising threshold temperature t otrth -150- c otp hysteresis t othys -25-c notes: 5. for EC7100VQI,there is one internal reference 0.5v an d there are four resistor-programmed reference voltages. 6. limits established by characteri zation and are not production tested. 7. parameters with min and/or max limits ar e 100% tested at +25c, unless otherwise specified. temperature limits established by characteriza- tion and are not production tested. electrical specifications all typical specifications t a = +25c, avin2 = 5v. boldface limits apply over the operating temperature range, -40c to +100c, unless otherwise stated. (continued) parameter symbol test conditions min (note 7) typ max (note 7) unit r t r set1 r set2 ? r set n ?? ++ = (eq. 1) t ss r t c soft ? ?? ? ln 1 v start-up i ss r t ? ----------------------------- - ? () ? = (eq. 2) 09613 march 14, 2014 rev a
page 9 EC7100VQI pwm dc/dc controller with vs inputs for fpga power regulator march 2014 altera corporation where: - i ss is the soft-start current source at the 17a limit -v start-up is the setpoint reference voltage selected by the state of the vs inputs at the time en is asserted -r t is the sum of the r set programming resistors the end of soft-start is detected by i ss tapering off when capacitor c soft charges to the designated v set voltage reference setpoint. the ssok flag is set, a nd the pok pin goes high. the i ss current source changes over to the voltage-step current source i vs which has a current limit of 85a. whenever the vs inputs or the external setpoint reference programs a different se tpoint reference voltage, the i vs current source charges or discharges capacitor c soft to that new level at 85a. once c soft charges to the selected setpoint voltage, the i vs current source comes out of the 85a current limit and decays to the static value set by v sref /r t . the elapsed time to charge c soft to the new voltage is called th e voltage-step delay t vs and is given by equation 3: where: - i vs is the 85a setpoint voltage -step current; positive when v new > v old , negative when v new < v old -v new is the new setpoint voltage selected by the vs inputs -v old is the setpoint voltage that v new is changing from -r t is the sum of the r set programming resistors choosing the c soft capacitor to meet the requirements of a particular soft-start delay t ss is calculated with equation 4, which is written as: where: - t ss is the soft-start delay - i ss is the soft-start current source at the 17a limit -v start-up is the setpoint reference voltage selected by the state of the vs inputs at the time en is asserted -r t is the sum of the r set programming resistors choosing the c soft capacitor to meet the requirements of a particular voltage-step delay t vs is calculated with equation 5, which is written as: where: - t vs is the voltage-step delay -v new is the new setpoint voltage -v old is the setpoint voltage that v new is changing from - i vs is the 85a setpoint voltage -step current; positive when v new > v old , negative when v new < v old -r t is the sum of the r set programming resistors output voltage programming the EC7100VQI allows the user to select four different refe rence voltages, thus four diff erent output voltages, by voltage identification pins vs1 and vs0. the ma ximum reference voltage cannot be designed higher than 1.5v. the implementation scheme is shown in figure 4. the setpoi nt reference voltages are programmed with resistors that use the naming convention r set(x) where (x) is the first, second, third, or fourth programming resistor connected in series starting at the sref pin and ending at the gnd pin. as shown in table 1, diff erent combinations of vs1 and vs0 close different switc hes and leave other switches open. for example, for th e case of vs1 = 1 and vs0 = 0, switch sw1 closes and all the ot her three switches sw0, sw2 and sw3 are open. for one co mbination of vs1 and vs0, t vs r t c soft ? ?? ? ln 1 v new v old ? ?? i vs r t ? ------------------------------------------- ? () ? = (eq. 3) c soft t ss ? r t ln 1 v start-up i ss r t ? ----------------------------- - ? () ? ?? ?? ?? --------------------------------------------------------------------- = (eq. 4) c soft t vs ? r t ln 1 v new v old ? i vs r t ? -------------------------------------- - ? () ? ?? ?? ?? ------------------------------------------------------------------------------ = (eq. 5) 09613 march 14, 2014 rev a
page 10 EC7100VQI pwm dc/dc controller with vs inputs fo r fpga power regulator march 2014 altera corporation the internal switch connects the inverting input of the v set amplifier to a specific node among the string of r set programming resistors. all the resistors between that node and the sref pin serve as the feedback impedance r f of the v set amplifier. likewise, all the resistors betw een that node and the gnd pin serve as the input impedance r in of the v set amplifier. equation 6 gives the general form of the gain equation for the v set amplifier: where: -v ref is the 0.5v internal reference of the ic -v setx is the resulting setpoint reference voltage that appears at the sref pin equations 7, 8, 9 and 10 give the specific v set equations for the EC7100VQI setpoint reference voltages. the EC7100VQI v set1 setpoint is written as equation 7: the EC7100VQI v set2 setpoint is written as equation 8: the EC7100VQI v set3 setpoint is written as equation 9: the EC7100VQI v set4 setpoint is written as equation 10: the v set1 is fixed at 0.5v becaus e it corresponds to the closure of inte rnal switch sw0 that configures the v set amplifier as a unity-gain voltage follower for the 0.5v voltage reference v ref . the setpoint reference volta ges use the naming convention v set(x) where (x) is the first, second, third, or fourth setpoint re ference voltage where: -v set1 < v set2 < v set3 < v set4 thus, -v out1 < v out2 < v out3 < v out4 for given four user selected reference voltages v setx , the programmed resistors r set1 , r set2 , r set3 and r set4 are designed in the following way. first, assi gn an initial value to r set4 of approximately 100k ? then calculate r set1, r set2 and r set3 using equations 11, 12, and 13 respectively. table 1. EC7100VQI vs truth table vs state result vs1 vs0 close v sref v out 11s w 0v set1 v out1 10s w 1v set2 v out2 01s w 2v set3 v out3 00s w 3v set4 v out4 v setx v ref 1 r f r in --------- - + ?? ?? ?? ? = (eq. 6) v set1 v ref = (eq. 7) v set2 v ref 1 r set1 r set2 r set3 r set4 ++ -------------------------------------------------------------------- - + ?? ?? ?? ? = (eq. 8) v set3 v ref 1 r set1 r set2 + r set3 r set4 + ------------------------------------------- - + ?? ?? ?? ? = (eq. 9) v set4 v ref 1 r set1 r set2 r + set3 + r set4 -------------------------------------------------------------------- - + ?? ?? ?? ? = (eq. 10) r set1 r set4 v set4 v set2 v ref ? ?? ?? v ref v set2 ? ------------------------------------------------------------------------------------------ - = (eq. 11) r set2 r set4 v set4 v set3 v set2 ? ?? ?? v set2 v set3 ? ---------------------------------------------------------------------------------------------- = (eq. 12) r set3 r set4 v set4 v set3 ? ?? ? v set3 ---------------------------------------------------------------------- - = (eq. 13) 09613 march 14, 2014 rev a
page 11 EC7100VQI pwm dc/dc controller with vs inputs for fpga power regulator march 2014 altera corporation the sum of all the programming resi stors should be approximately 300k ?? as shown in equation 14, ot herwise adjust the value of r set4 and repeat the calculations. if the output voltage is in the range of 0.5v to 1.5v, the external resistor-divider is not necessary. the output voltage is eq ual to one of the reference voltages depending on th e status of vs1 and vs0. the extern al resistor divide r consisting of r fb and r ofs allows the user to program the output voltage in the range of 1.5v to 5v. th e relation between the output voltage and the reference is given in equation 15: in this case, the four output voltages ar e equal to each of the co rresponding reference voltages mu ltiplying the factor k. high output voltage programming the EC7100VQI has a fixed 0.5v reference voltage (v sref ). for high output voltage application, the resist or divider consisting of r fb and r ofs requires large ratio (r fb :r ofs = 9:1 for 5v output). the fb pin with large ratio resistor divider is noise sensitive and the pcb layout should be care fully routed. it is recommended to use small value resistor divider such as r fb =1k ?? modulator the modulator allows variable frequency in response to load transients and maintain s the benefits of cu rrent-mode hysteretic controllers. however, in additi on, the modulator reduces regulator output impedance and uses accu rate referenci ng to eliminate the need for a high-gain voltage am plifier in the compensation loop. the result is a topology that can be tuned to voltage-mode hysteretic transient speed while maintaining a linear control m odel and removes the need for a ny compensation. this greatly simplifies the regulator de sign for customers and reduces external component cost. r set1 r set2 r set3 r set4 +++ 300k ?? (eq. 14) figure 4. EC7100VQI voltage programming circuit set2 set0 sref v set ? ? sw0 v ref set1 sw1 sw2 sw3 c soft r set1 r set2 r set3 r set4 ea ? ? fb r ofs r fb v out v comp 0.5v v out v sref r fb r ofs + r ofs --------------------------------- - ? v sref k ? == (eq. 15) v outx v setx k ? = (eq. 16) 09613 march 14, 2014 rev a
page 12 EC7100VQI pwm dc/dc controller with vs inputs fo r fpga power regulator march 2014 altera corporation stability the removal of compensation derives from the modulator?s lack of need for high dc gain. in trad itional architectures, high dc g ain is achieved with an integrator in the volta ge loop. the integrator introduces a pole in the open-loop tran sfer function at low frequencies. that, combined with the double-pole from the output l/c filter, creates a three pole system that must be compensat ed to maintain stability. classic control theory requires a single-pole transition through unity gain to ensure a stable system. current-mode architectur es (includes peak, peak-valley, curre nt-mode hysteretic) generate a ze ro at or near the l/c resona nt point, effect ively canceling one of the system?s poles. the system still contains two poles, one of wh ich must be canceled with a ze ro before unity gain crossover to achieve stability. compensation components ar e added to introduce the necessary zero. figure 5 illustrates the classic integrator configuration for a voltage loop error-ampl ifier. while the integrator provides the high dc gain required for accurate regulation in traditional technologies, it also introduces a low-frequency pole into the control loo p. figure 6 shows the open-loop response that results from the addition of an integrat ing capacitor in the voltage loop. the compensation components found in figure 5 are necessary to achieve stability. because the modulator does not requi re a high-gain voltage loop, th e integrator can be removed, reducing the number of inherent poles in the loop to two. the current-mode zero continues to cancel one of the pol es, ensuring a single-po le crossover for a wi de figure 5. integrator error-amplifier configuration v v comp integrator for high dc gain compensation to counter integrator pole v out v dac v comp figure 6. uncompensated integrator open-loop response f (hz) p1 p2 p3 l/c double-pole integrator pole z1 zero - 6 0 d b / d e c - 2 0db/dec -20db crossover required for stability compensator to add z2 is needed - 4 0 d b / d e c r3 loop gain (db) current-mode 09613 march 14, 2014 rev a
page 13 EC7100VQI pwm dc/dc controller with vs inputs for fpga power regulator march 2014 altera corporation range of output filter choices. the result is a stable system wi th no need for compensation components or complex equations to properly tune the stability. figure 7 shows the error-amplifier that does not require an integr ator for high dc gain to achiev e accurate regulation. the res ult to the open loop response can be seen in figure 8. transient response in addition to requiring a compensation zero, the integrator in traditional architecture s also slows system response to transie nt conditions. the change in comp voltage is slow in response to a rapid change in ou tput voltage. if the integrating capacitor is removed, comp moves as quickly as vout, and the modulat or immediately increases or de creases switching frequency to recover the output voltage. diode emulation the polarity of the output inductor current is defined as positive when conducting aw ay from the switch node, and defined as negative when conducting towards the switch node. the dc component of the inductor current is positive, but the ac component known as the ripple current, can be either positive or negative. should the sum of the ac and dc components of the inductor current remain positive for the entire switc hing period, the converter is in conti nuous-conduction-mode (ccm). however, if the inductor current becomes negative or zero, the converter is in discontinuous-conductio n-mode (dcm). unlike the standard dc/dc buck regulator, the synchronous rectifier can sink current from the output filter inductor during dcm , reducing the light-load efficiency with unnecessary conduction loss as the low-side mosfet sinks the inductor current. the EC7100VQI controllers avoid the dcm conduction loss by making th e low-side mosfet emulate th e current-blocking behavior of a diode. this smart-diode operation ca lled diode-emulation-mode (dem) is trigge red when the negative inductor current produces a positive voltage drop across the r ds(on) of the low-side mosfet for eight c onsecutive pwm cycles while the lgate pin is high. the converter will exit dem on the next pwm pulse after dete cting a negative voltage across the r ds(on) of the low- side mosfet. it is characteristic of the architecture for the pwm switchi ng frequency to decrease while in dcm, increasing efficiency by reducing unnecessary gate-driver sw itching losses. the extent of the frequency re duction is proportional to the reduction of lo ad current. upon entering dem, the pwm frequency is forced to fall approximately 30% by forcing a similar increase of the window voltage v w . this measure is taken to preven t oscillating betwee n modes at the boundary betw een ccm and dcm. the 30% figure 7. non-integrated error-amplifier configuration v out v dac r1 r2 v comp figure 8. uncompensated open-loop response f (hz) p1 p2 l/c double-pole z1 current-mode zero -20db/dec system has 2 poles and 1 zero no compensator is needed loop gain (db) - 20 d b / d ec - 4 0 d b / d e c 09613 march 14, 2014 rev a
page 14 EC7100VQI pwm dc/dc controller with vs inputs fo r fpga power regulator march 2014 altera corporation increase of v w is removed upon exit of dem, forc ing the pwm switching frequency to ju mp back to the nominal ccm value. overcurrent the overcurrent protection (ocp) setpoint is progr ammed with resistor r ocp , which is connected acro ss the ocp and sw pins. resistor r o is connected between the vsns pin and the actual output voltage of the converter. during normal operation, the vsns pin is a high impedance path, therefore there is no voltage drop across r o . the value of resistor r o should always match the value of resistor r ocp . figure 9 shows the overcurrent set circuit. the inductor consists of inductance l and the dc resistance dcr. the inductor dc current i l creates a voltage drop across d cr, which is given by equation 17: the i ocp current source sinks 8.5a into the ocp pin, creating a dc voltage drop across the resistor r ocp , which is given by equation 18: the dc voltage difference between the ocp pin a nd the vsns pin, which is given by equation 19: the ic monitors the voltage of the ocp pin and the vsns pin. when the voltage of the ocp pin is higher than the voltage of the vsns pin for more than 10s, an oc p fault latches the converter off. the value of r ocp is calculated with equation 20, which is written as: where: -r oc ( ? ) is the resistor used to pr ogram the overcurrent setpoint -i oc is the output dc load current that wi ll activate the ocp fa ult detection circuit - dcr is the inductor dc resistance for example, if i oc is 20a and dcr is 4.5m ? , the choice of r ocp is equal to 20a x 4.5m ? /8.5a = 10.5k ?? resistor r ocp and capacitor c sen form an r-c network to sense the inductor curre nt. to sense the inductor current correctly not only in dc operation, but also during dynamic operation, the r- c network time constant r ocp c sen needs to match the inductor time constant l/dc r. the value of c sen is then written as equation 21: for example, if l is 1.5h, dcr is 4.5m ? , and r ocp is 9k ??? the choice of c sen = 1.5h/(9k?? x 4.5m ? ) = 0.037f ? when an ocp fault is declared, the converter will be latched off and the pok pin will be asserted low. the fault will remain latched until the en pin has been pulled below the falling en threshold voltage v enthf or if avin2 has decayed below the falling por threshold voltage v av i n 2 _ t h f . figure 9. overcurrent programming circuit sw c o l v out r ocp c sen ocp vsns r o dcr i l 8.5a + _ v dcr + _ v rocp v dcr i l dcr ? = (eq. 17) v rocp 8.5 ? ar ocp ? = (eq. 18) v ocp v ? vo v dcr v ? rocp i l dcr ? i ocp r ocp ? ? == (eq. 19) (eq. 20) r oc i oc dcr ? i ocp ---------------------------- = (eq. 21) c sen l r ocp dcr ? ---------------------------------- - = 09613 march 14, 2014 rev a
page 15 EC7100VQI pwm dc/dc controller with vs inputs for fpga power regulator march 2014 altera corporation overvoltage the ovp fault detection circuit trigge rs after the fb pin voltage is above the rising overvoltage threshold v ovrth for more than 2s. for example, if the converter is progr ammed to regulate 1.0v at the fb pin, that voltage w ould have to rise above the typi cal v ovrth threshold of 116% for more than 2s in order to trip the ovp fault latch. in numer ical terms, th at would be 116% x 1.0v = 1.16v. when an ovp fault is declared, the converter will be latched off and the pok pin will be asserted low. the fault will remain latche d until the en pin has been pulled be low the falling en threshold voltage v enthf or if avin2 has decayed below the falling por threshold voltage v avin2_thf . although the converter has latched-of f in response to an ovp fault, the lgate gate-driver output wi ll retain the ability to tog gle the low-side mosfet on and off, in respons e to the output voltage transversing the v ovrth and v ovfth thresholds. the lgate gate-driver will turn-on the low-side mo sfet to discharge the output voltage, protec ting the load. the lgate gate-driver will turn-off the low-side mosfet once the fb pin voltage is lower than the falli ng overvoltage threshold v ovrth for more than 2s. the falling overvoltage threshold v ovfth is typically 102%. that means if the fb pin voltage falls below 102% x 1.0v = 1.02v for more than 2s, the lgate gate-driver will turn off the low-side mosfet. if the output voltage rises again, the lgate driver wil l again turn on the low-side mosfet when the fb pin voltage is above the rising overvoltage threshold v ovrth for more than 2s. by doing so, the ic protects the load when there is a consistent overvoltage condition. undervoltage the uvp fault detection circuit trig gers after the fb pin voltage is below the undervoltage threshold v uvth for more than 2s. for example if the converter is programmed to regulate 1.0v at the fb pin, that voltage would have to fall below the typical v uvth threshold of 84% for more than 2s in order to trip the uvp fault latch. in numerical terms, that would be 84% x 1.0v = 0.84v. when a uvp fault is declared, the converter will be latched off and the pok pin will be asserted low. the fault will remain latched until the en pin has been pulled below the falling en threshold voltage v enthf or if avin2 has decayed below the falling por threshold voltage v avin2_thf . over-temperature when the temperature of the ic increase s above the rising threshold temperature t otrth , it will enter the otp state that suspends the pwm, forcing the lgate and ugate gate-drive r outputs low. the status of the pok pin does not change nor does the converter latc h- off. the pwm remains suspended until the ic temp erature falls below the hysteresis temperature t othys at which time normal pwm operation resumes. the otp st ate can be reset if the en pin is pulle d below the falling en threshold voltage v enthf or if avin2 has decayed below the falling por threshold voltage v avin2_thf . all other protection circuits remain functional while the ic is in the otp state. it is likely that the ic will detect an uvp fault beca use in the absence of pwm, the output voltage deca ys below the und ervoltage threshold v uvth . pok monitor the pok pin indicates when the converter is capable of supplying regulated voltage. the pok pin is an undefined impedance if th e av i n 2 p i n has not reached the rising por threshold v avin2_thr , or if the avin2 pin is below the falling por threshold v avin2_thf . if there is a fault condition of output overcurrent, overvoltage or undervoltage, pok is asserted low. the pok pull-down impedance is 50 ??? integrated mosfet gate-drivers the lgate pin and ugate pins are mosfet driver outputs. the lgate pin drives the low-side mosfet of the converter while the ugate pin drives the hi gh-side mosfet of the converter. the lgate driver is optimized for low duty-cycle applications where the low-si de mosfet experiences long conduction times. in this environment, the low-side mosfets require exceptionally low r ds(on) and tend to have large parasitic charges that conduct transient currents within the devices in response to high dv/dt switching pres ent at the switch node. the drain-gate ch arge in particular can conduct sufficie nt current through the driver pull-down resistance that the v gs(th) of the device can be exceeded and turned on. for this reason, the lgate driver has been desi gned with low pull-down resistan ce and high sink current capabili ty to ensure clamping the mosf ets gate voltage below v gs(th) . adaptive shoot-through protection adaptive shoot-through protection prevents a gate-driver output from turning on until the opposite gate-driver ou tput has falle n below approximately 1v. the dead-time shown in figure 10 is ex tended by the additional period that the falling gate voltage remains above the 1v thre shold. the high-side gate-driver output voltage is measured across the ugate and sw pins while the low-side gate-driver output voltage is measured across the lgate and pgnd pins. the power for the lgate gate-driver is sourced directly from the avin1 pin. the- power for the ugate gate-driver is supplie d by a boot-strap capaci tor connected across 09613 march 14, 2014 rev a
page 16 EC7100VQI pwm dc/dc controller with vs inputs fo r fpga power regulator march 2014 altera corporation the boot and sw pins. the capaci tor is charged each time the sw itch node voltage falls a diode drop below avin1 such as when the low-side mosfet is turned on. general application design guide this design guide is intended to provide a high-level explanation of the steps necessa ry to design a single-phase buck converte r. it is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. in addition to th is guide, altera provides complete re ference designs that include schematics, bill s of materials, and example board layouts. selecting the lc output filter the duty cycle of an ideal buck converter is a function of the input and the output voltage. this relationship is expressed in equation 22: the output inductor peak-to-peak ripple current is expressed in equation 23: a typical step-down dc/dc c onverter will have an i pp of 20% to 40% of the maximum dc output load current. the value of i p-p is selected based upon several criteria su ch as mosfet switching loss, inductor core loss, and the resistive loss of the induct or winding. the dc copper loss of the inductor can be estimated using equation 24: where, i load is the converter output dc current. the copper loss can be significant so attention has to be given to the dcr of the inductor. another factor to consider when choosing the inductor is its saturation charac teristics at elevated temperature. a sa turated inductor could cause destruction o f circuit components, as well as nuisance ocp faults. a dc/dc buck regulator must have output capacitance c o into which ripple current i p-p can flow. current i p-p develops a corresponding ripple voltage v p-p across c o, which is the sum of the voltage drop across the capacitor esr and of the voltage change stemming from charge moved in a nd out of the capacitor. these two volta ges are expressed in equations 25 and 26: figure 10. gate drive adapti ve shoot-through protection 1v 1v ugate lgate 1v 1v d v out v in --------------- - = (eq. 22) (eq. 23) i p-p v out 1d ? ?? ? f sw l ? -------------------------------------- - = (eq. 24) p copper i load 2 dcr ? = ? v esr i p-p e ? sr = (eq. 25) ? v c i p-p 8c o f ? sw ? --------------------------------- = (eq. 26) 09613 march 14, 2014 rev a
page 17 EC7100VQI pwm dc/dc controller with vs inputs for fpga power regulator march 2014 altera corporation if the output of the converter has to support a load w ith high pulsating current, several capacitors will need to be paralleled to reduce the total esr until the required v p-p is achieved. the inductance of th e capacitor can significantly impact the output voltage ripple and cause a brief voltage spike if the load tr ansient has an extremely high slew rate. low inductance capacitors should be consider ed. a capacitor dissipates heat as a function of rms current and frequency. be sure that i p-p is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated rms current at f sw . take into account that the rated value of a capacitor can fade as much as 50% as the dc voltage across it increases. selecting the input capacitor the important parameters for th e bulk input capacitors are the voltage rating and the rms current rating. for reliable operatio n, select bulk capacitors with vo ltage and current ratings above the maximum input voltage and capable of supplying the rms current required by the switching circuit. their voltage rating should be at least 1.25x greater than the maximum input voltage , while a voltage rating of 1.5x is a preferred rating. figure 11 is a graph of the input rms ripple current, normalized relative to output load current, as a function of duty cycle that is adjusted for converter effi ciency. the ripple current calculation is written as equation 27: where: -i max is the maximum continuous i load of the converter - x is a multiplier (0 to 1) corresponding to the inductor pe ak-to-peak ripple amp litude expressed as a percentage of i max (0% to 100%) - d is the duty cycle that is adjusted to take into account the efficiency of the converter duty cycle is wri tten as equation 28: in addition to the bulk capacito rs, some low esl ceramic capacitors are recomm ended to decouple between the drain of the high- side mosfet and the source of the low-side mosfet. selecting the bootstrap capacitor the integrated driver features an internal bootstrap schottky diod e. simply adding an external capacitor across the boot and sw pins completes the bootstrap circui t. the bootstrap capacitor voltage rating is selected to be at least 10v. although the theor etical (eq. 27) i in_rms i max 2 dd 2 ? ?? ? ?? x 2 i max 2 d 12 ------ ?? ?? ?? + i max -------------------------------------------------------------------------------------------------------- = (eq. 28) d v out v in eff ? -------------------------- = figure 11. normalized input rms current for eff = 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 duty cycle normalized input rms ripple current x = 0.5 x = 0 x = 1 09613 march 14, 2014 rev a
page 18 EC7100VQI pwm dc/dc controller with vs inputs fo r fpga power regulator march 2014 altera corporation maximum voltage of the capacitor is avin1-v diode (voltage drop across the boot diode), large excursions below ground by the switch node requires at least a 10v rating for the bootstrap capacitor. the bootstrap capacitor can be chosen from equation 29: where: -q gate is the amount of gate char ge required to fully charge the gate of the upper mosfet - ? v boot is the maximum decay across the boot capacitor as an example, suppose the high-side mosfet has a total gate charge q g , of 25nc at v gs =5v, and a ? v boot of 200mv. the calculated bootstrap capaci tance is 0.125f; for a comfortable margin, select a capacitor that is double the calculated capacit ance. in this example, 0.22f will suffice. use a low temperature-coefficient ceramic capacitor. driver power dissipation switching power dissipation in the driver is mainly a function of the switching frequency and tota l gate charge of the selected mosfets. calculating the power dissipati on in the driver for a desired applicati on is critical to ensu ring safe operation. exceeding the maximum allowable power dissipation level will push the ic beyond the maximum re commended operating junction temperature of +125c. when designi ng the application, it is recommended that the following calcula tion be performed t o ensure safe operation at the desired frequen cy for the selected mosfets. the power dissipated by the drivers is approximated as equation 30: where: -f sw is the switching frequency of the pwm signal -v u is the upper gate driver bias supply voltage -v l is the lower gate dr iver bias supply voltage -q u is the charge to be de livered by the upper driver into the gate of the mosfet and discrete capacitors -q l is the charge to be delivered by the lower driver into the gate of the mosfet and discrete capacitors -p l is the quiescent power consumption of the lower driver -p u is the quiescent power co nsumption of the upper driver mosfet selection and considerations the choice of mosfets depends on the current each mosfet will be required to conduct, the switching frequency, the capability of the mosfets to dissipate heat, and the av ailability and natu re of heat sinking and air flow. c boot q gate ? v boot ----------------------- - ? (eq. 29) pf sw 1.5v u q u v l q l + ?? p l p u ++ = (eq. 30) figure 12. power dissipation vs frequency frequency (hz) 0 100 200 300 400 500 600 700 800 900 1000 0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k power (mw) q u =50nc q l =50nc q u =20nc q l =50nc q u =50nc q l =100nc q u =100nc q l =200nc 09613 march 14, 2014 rev a
page 19 EC7100VQI pwm dc/dc controller with vs inputs for fpga power regulator march 2014 altera corporation typically, a mosfet cannot tolerate even brief excursions beyond their maximum drai n to source voltage rating. the mosfets used in the power stage of the converter should have a maximum v ds rating that exceeds the sum of the upper voltage tolerance of the input power source and the voltage spik e that occurs when the mosfets switch. there are several power mosfets readily avai lable that are optimized fo r dc/dc converter applicatio ns. the preferred high-side mosfet emphasizes low gate charge so that the device spends th e least amount of time dissipati ng power in the linear region. the preferred low-side mosfet emphasizes low r ds(on) when fully saturated to minimize conduction loss. for the low-side mosfet, (ls), the power loss can be a ssumed to be conductive only an d is written as equation 31: for the high-side mosfet, (hs), its c onduction loss is written as equation 32: for the high-side mosfet, its switchi ng loss is written as equation 33: where: -i valley is the difference of the dc component of the i nductor current minus 1/2 of the inductor ripple current -i peak is the sum of the dc component of the inducto r current plus 1/2 of the inductor ripple current -t on is the time required to drive the device into saturation -t off is the time required to drive the device into cut-off layout considerations as a general rule, power layers should be close together, either on the top or bottom of the board, with the weak analog or log ic signal layers on the opposite side of the board. the ground-plane layer should be adjacent to the signal layer to provide shiel ding. the ground plane layer should have an isla nd located under the ic, the components conne cted to analog or logic signals. the island should be connected to the rest of the ground plane layer at one quiet point. there are two sets of components in a dc/dc converter, the power components and the small signal components. the power components are the most critical because th ey switch large amount of energy. the smal l signal components c onnect to sensitive nodes or supply critical bypassing current and signal coupling. the power components should be placed fi rst and these include mosfets, input and out put capacitors, and the inductor. keeping the distance between the power train and the control ic short help s keep the gate drive traces s hort. these drive signals inclu de the lgate, ugate, pgnd, sw and boot. when placing mosfets, try to keep the source of the upper mo sfets and the drain of the lower mosfets as close as thermally possible. see figure 13. input high frequency capacitors should be placed close to th e drain of the upper mosfets and the sourc e of the lower mosfets. place the output inductor and output ca pacitors between the mosfets and the load. high frequency output decoupling capacitors (cer amic) should be placed as clos e as possible to the decoupling target, making use of the shorte st (eq. 31) p con_ls i load 2 r ? ds on ?? _ls 1d ? ?? ? ? (eq. 32) p con_hs i load 2 r ? ds on ?? _hs d ? = (eq. 33) p sw_hs v in i valley t on f ? sw ?? 2 --------------------------------------------------------------------- - v in i peak t off f ? sw ?? 2 ----------------------------------------------------------------- - + = figure 13. typical power component placement sw 09613 march 14, 2014 rev a
page 20 EC7100VQI pwm dc/dc controller with vs inputs fo r fpga power regulator march 2014 altera corporation connection paths to any internal planes. pl ace the components in such a way that the area under the ic has less noise traces wi th high dv/dt and di/dt, such as gate signals and switch node signals. avin2 and avin1 pins place the decoupling capacitors as close as practical to the ic. in particular , the avin1 decoupling ca pacitor should have a ve ry short and wide connection to the pgnd pin. the avin2 decoupling capacitor should be refere nced to gnd pin. en, pok, vs0, vs1, and fsw pins these are logic signals that are referenced to the gnd pin. treat as a typical logic signal. ocp and vsns pins the current-sensing network consisting of r ocp , ro, and csen needs to be connecte d to the inductor pads for accurate measurement of the dcr voltage drop. thes e components however, should be located physi cally close to the ocp and vsns pins with traces leading back to the inductor. it is critical that the traces are shie lded by the ground plane layer all the way to the inductor pads. the procedure is the same for resistiv e current sense. fb, sref, set0, set1, set2, and nsns pins the input impedance of these pins is high, making it critical to place the components connected to these pins as close as possi ble to the ic. lgate, pgnd, ugate, boot, and sw pins the signals going through these traces are hi gh dv/dt and high di/dt, with high peak charging and discharging current. the pgnd pin can only flow current from th e gate-source charge of the low-side mosfets when lgate goes low. ideally, route the trace from the lgate pin in parallel with the trace from the pgnd pin, route the trace from the ugate pin in parallel with the trace from the sw pin. in order to have more ac curate zero-crossing detection of inductor cu rrent, it is recomme nded to connect sw pi n to the drain of the low-side mosfets with kelvin connection. these pairs of traces s hould be short, wide, and away from other traces with high input impedance; weak signal traces should not be in prox imity with these traces on any layer. document revision history the table lists the revision history for this document. date version changes march 2014 1.0 initial release. 09613 march 14, 2014 rev a
pag e 2 1 EC7100VQI pwm dc/dc controller with vs inputs fo r fpga power regulator march 2014 altera corporation package outline drawing l20.3x4 20 lead quad flat no-lead plastic package typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is m easured di mensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 0.10 m c a b mc 0.05 0.15 0.08 c 0.10 c a b c c 4.00 3.00 20x 0.400.10 2.65 1.65 0.25 0.50 (2.80) (1.65) +0.10 -0.15 +0.10 -0.15 +0.05 -0.07 20x a a 4 (4x) seating plane 0.9 0.10 5 0.2 ref 0.05 max. see detail "x" 0.00 min. (c 0.40) 1 20 17 16 11 6 10 7 (3.80) (2.65) (20 x 0.25) (20 x 0.60) (16 x 0.50) 16x view "a-a" pin 1 index area pin 1 index area 09613 march 14, 2014 rev a

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